HW Security Engineer

As an ASIC Security Engineer, you will help architect and develop security IPs such as post-quantum crypto accelerators and random-number generators within Rambus's Security IP team. You collaborate with system architects, software, product managers, and security experts to shape secure crypto cores and ensure quality and safety standards. The role sits at the intersection of hardware design and security, offering impact across certification efforts and next-generation products. You will contribute to a culture of innovation, safety, and configurable silicon IP in a hybrid work environment. This is a chance to work with top engineers on security-centric hardware that advances data protection

• hybrid work model
• base salary
• bonus
• equity
• employee benefits

• Research, invent and publish new security techniques
• Contribute to architecture and design of crypto cores with system architects
• Collaborate with software, product management, and security stakeholders to support current and next-generation products and certification
• Drive design improvements for product quality and safety
• Ensure delivered products and documentation meet Rambus quality and safety standards

• 4+ years in secure hardware design (PhD may substitute experience)
• Proficiency in Verilog (or VHDL) and digital design
• Familiarity with front-end ASIC design flows: design, synthesis, timing, LEC, linting
• Unix/Linux hardware development experience with shell scripting and basic Perl
• Desirable: cryptographic algorithms, side-channel attacks, back-end flows (P&R), DFT/Logic BIST, testing and characterization

• collaboration
• initiative
• problem-solving
• Verilog/SystemVerilog
• VHDL
• cryptographic algorithms