ASIC Verification Engineer

ASIC Verification Engineer

Fortaegis is a fast-scaling, highly ambitious and cutting-edge semiconductor company. We are looking for an experienced ASIC Verification Engineer to join the hardware engineering team. As a Verification Engineer, you will play a key role in ensuring the quality and reliability of our cutting-edge products. Leveraging your extensive experience with Universal Verification Methodology (UVM) and verification techniques, you will contribute to the development of robust verification environments and methodologies. You will collaborate closely with cross-functional teams including design, architecture and software engineering to deliver high-quality solutions that meet or exceed customer expectations. We are looking for candidates with not only an exceptional skillset, but also an exceptional mindset, willing to go above and beyond to make our breakthrough product even better.

Responsibilities:

• Develop and maintain UVM-based verification environments for complex digital designs.
• Create comprehensive verification plans and test cases based on design specifications.
• Implement and execute test benches to verify functionality, performance, and compliance with specifications.
• Debug issues and work closely with design engineers to resolve them in a timely manner.
• Drive continuous improvement of verification methodologies, processes, and best practices.
• Collaborate with other teams to ensure alignment of verification efforts with project timelines and goals.
• Participate in design reviews and contribute to architectural decisions from a verification perspective.

Requirements:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field. A master's degree is a plus.
• Minimum of 5 years of experience in ASIC verification.
• Expert understanding of logic design and verification
• Development and deployment of large SoCs on emulation platforms
• Practical experience of verifying on processor-based system designs
• Experience verifying subsystems for PCIe, DDR, UCIe, Ethernet
• Knowledge of C/C++ and/or hardware verification languages e.g. (SystemVerilog, SystemC), shell programming/scripting (e.g. Tcl, Perl, Python etc.)
• Experienced in one or more of various verification methodologies – UVM, formal, emulation
• Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation and support
• Knowledge of HW/SW Co-simulation/emulation and QEMU are nice to have, but we will consider applicants without this experience.

The successful candidate will have the unique opportunity to participate in shaping the verification infrastructure and processes from the ground up, contributing to the development

of ultra-secure and high-performance SoC designs. They will be part of a highly motivated, dynamic and innovative team, working in a collaborative and challenging environment at the

forefront of semiconductor technology.